============================================================== Guild: wafer.space Community Channel: Information / general / Ah, this reminds me I wanted to start After: 02/28/2026 23:59 Before: 04/01/2026 00:00 ============================================================== [03/20/2026 11:54] tholin [03/20/2026 11:54] tholin The idea is that you just specify a projects.yaml listing the projects you have, as well as having each LibreLane project in its own directory, and then the tool automatically clones the template repo, generates a top-level config, generates the multiplexer verilog source and runs the flow. [03/20/2026 11:55] tholin {Attachments} 2026-03_media/image-30C93.png [03/20/2026 11:56] tholin pin mapping is a long list showing how a design’s module outputs map to the pads when selected [03/20/2026 11:56] tholin You can actually map these connections arbitrarily [03/20/2026 11:57] tholin Consider this design, where I wish to save on signals by not having enables for every pad {Attachments} 2026-03_media/image-5F410.png [03/20/2026 11:57] tholin Which I can then map like this {Attachments} 2026-03_media/image-0D154.png [03/20/2026 11:58] tholin If the number of outputs of a design is equal to the total number of outputs available, there is a special shorthand syntax where you just type "out" for a 1:1 mapping, such that ``` 1: out[1] 2: out[2] 3: out[3] ``` is equivalent to just ``` 1: out 2: out 3: out ``` [03/20/2026 11:59] tholin If you have less outputs, you need an explicit mapping, though [03/20/2026 12:00] tholin As for inputs, there is no mapping. Every design receives all available inputs always. [03/20/2026 12:00] tholin This solution has worked for me for many tapeouts [03/20/2026 12:03] tholin (And, of course, the syntax of `in_pu` just means constant input with pull-up) [03/20/2026 12:03] tholin The syntax is pretty simple. Its just a list of attributes separated by underscores [03/20/2026 12:04] tholin {Attachments} 2026-03_media/projects-FBC0B.yaml [03/20/2026 12:05] tholin TODO: allow the placement of arbitrary macros with connections between them so you can, for instance, have SRAM macros on your multi-project die [03/20/2026 13:33] tholin Is there any python library I can use to help me procedurally generate code, or is there some preferred way to do this? ============================================================== Exported 16 message(s) ==============================================================